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1 MX23L6454 64m-bit low voltage, serial mask rom memory with 50mhz spi bus interface features ? 64mbit of mask rom 2.7 to 3.6v single supply voltage spi bus compatible serial interface 50mhz clock rate (maximum) description the MX23L6454 is a 64mbit serial mask rom accessed by a high speed spi-compatible bus. pin configurations symbol description c serial clock d serial data input q serial data output s# chip select hold# hold vcc supply voltage vss ground pin description 16-pin sop (300 mil) 1 2 3 4 5 6 7 8 hold# vcc nc nc nc nc s# q 16 15 14 13 12 11 10 9 c d nc nc nc nc vss nc note: 1. nc=no connection 2. see page 16 (onwards) for package dimensions, and how to identify pin-1. p/n: pm1127 rev. 1.1, mar. 09, 2005 order information part no. speed package remark MX23L6454mc-20 20ns 16-sop MX23L6454mc-20g 20ns 16-sop pb-free MX23L6454mi-20g 20ns 16-sop pb-free (industrial grade) note: * industrial grade operating temperature: -25 ~ 85 c commercial grade operating temperature: 0 ~ 70 c .com .com .com 4 .com u datasheet
2 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 memory organization the memory is organized as 8m bytes block diagram hold# s# control logic i/o shift register address register and counter 256 byte data buffer x decoder y decoder size of the read-only memory area c d q .com .com .com .com 4 .com u datasheet
3 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 signal description serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives instructions, addresses. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s#). when this input signal is high, the device is deselected. driving chip select (s#) low ena- bles the device, placing it in the active power mode. after power-up, a falling edge on chip select (s#) is required prior to the start of any instruction. hold (hold#). the hold (hold#) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don't care. to start the hold condition, the device must be selected, with chip select (s#) driven low. .com .com .com .com 4 .com u datasheet
4 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: - cpol=0, cpha=0 - cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 2, is the clock polarity when the bus master is in stand-by mode and not transferring data: - c remains at 0 for (cpol=0, cpha=0) - c remains at 1 for (cpol=1, cpha=1) figure 1. bus master and memory devices on the spi bus note: 1. hold (hold#) signals should be driven, high or low as appropriate. figure 2. spi modes supported bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd spi memory device cqd spi memory device cqd s# cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) hold# s# hold# s# hold# c msb cpha d 0 1 cpol 0 1 q c msb .com .com .com .com 4 .com u datasheet
5 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 operating features active power, stand-by power when chip select (s#) is low, the device is enabled, and in the active power mode. when chip select (s#) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed. the device then goes in to the stand-by power mode. the device consumption drops to icc1 . protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the MX23L6454 boasts the following data protection mechanisms: - power-on reset and an internal timer (tpuw) can provide protection against inadvertant changes while the power supply is outside the operating specification. hold condition the hold (hold#) signal is used to pause any serial communications with the device without resetting the clocking sequence. to enter the hold condition, the device must be selected, with chip select (s#) low. the hold condition starts on the falling edge of the hold (hold) signal, provided that this coincides with serial clock (c) being low (as shown in figure 3). the hold condition ends on the rising edge of the hold (hold#) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts after serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condi- tion ends after serial clock (c) next goes low. (this is shown in figure 2). during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don't care. normally, the device is kept selected, with chip select (s#) driven low, for the whole duration of the hold condi- tion. this is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select (s#) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart communication with the device, it is necessary to drive hold (hold#) high, and then to drive chip select (s#) low. this prevents the device from going back to the hold condition. figure 3. hold condition activation (for data output only) q4 q2 q1 q0 q c hold# hold# c q0 q1 q3 q4 q5 q2 q2 q3 q2 q5 q6 q .com .com .com .com 4 .com u datasheet
6 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s#) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 1. table 1. instruction set every instruction sequence starts with a one-byte instruc- tion code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), the shifted-in instruc- tion sequence is followed by a data-out sequence. chip select (s#) can be driven high after any bit of the data-out sequence is being shifted out. instruction description one-byte instruction code address bytes dummy bytes data bytes read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to .com .com .com .com 4 .com u datasheet
7 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 figure 4. read data bytes (read) instruction sequence and data-out sequence read data bytes (read) the device is first selected by driving chip select (s#) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency fr, during the falling edge of serial clock (c). the instruction sequence is shown in figure 4. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction.when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (s#) high. chip select (s#) can be driven high at any time during data output. note: 1. address bits a23 is don't care. c d s# q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2 .com .com .com .com 4 .com u datasheet
8 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 figure 5. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 c d s# q c d s# q read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s#) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3- byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency fc, during the falling edge of serial clock (c). the instruction sequence is shown in figure 5. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (s#) high. chip select (s#) can be driven high at any time during data output. .com .com .com .com 4 .com u datasheet
9 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s#) must follow the voltage applied on vcc ) until vcc reaches the correct value: - vcc(min) at power-up, and then for a further delay of tvsl - vss at power-down usually a simple pull-up resistor on chip select (s#) can be used to insure safe and proper power-up and power- down. to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while vcc is less than the por threshold value, vwi -- all operations are disabled, and the device does not respond to any instruction. these values are specified in table 2. figure 6. power-up timing if the delay, tvsl, has elapsed, after vcc has risen above vcc (min), the device can be selected for read instructions even if the tpuw delay is not yet fully elapsed. at power-up, the device is in the following state: - the device is in the standby mode. normal precautions must be taken for supply rail decoupling, to stablise the vcc feed. each device in a system should have the vcc rail decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 0.1uf). at power-down, when vcc drops from the operating voltage, to below the por threshold value, vwi , all operations are disabled and the device does not respond to any instruction. v cc v cc (min) v wi reset state of the device chip selection not allowed tvsl tpuw time read access allowed device fully accessible v cc (max) .com .com .com .com 4 .com u datasheet
10 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 table 2. power-up timing maximum rating stressing the device above the rating listed in the"absolute maximum ratings" table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. table 3. absolute maximum ratings note: 1. these parameters are characterized only. symbol parameter min. max. unit t vsl 1 v cc (min) to s# low 30 us note: 1. compliant with the ecopack ? 7191395 specifiication for lead-free soldering processes 2. not exceeding 250?c for more than 30 seconds, and peaking at 260?c 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature - 65 150 ?c t lead lead temperature during soldering 1 260 2 ?c v io input and output voltage (with respect to ground) v cc supply voltage v esd electrostatic discharge voltage (human body model) 3 - 2000 2000 v 4.0 v 4.0 v - 0.5 - 0.2 .com .com .com .com 4 .com u datasheet
11 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 dc and ac parameters this section summarizes the operating and mea-surement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic table 4. operating conditions table 5. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v figure 7. ac measurement i/o waveform 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels 0.5v cc table 6. capacitance tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating condi- tions in their circuit match the measurement conditions when relying on the quoted parameters. note: sampled only, not 100% tested, at t a =25 ? c and a frequency of 20 mhz. symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature -25 85 ? c .com .com .com .com 4 .com u datasheet
12 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 table 7. dc characteristics symbol parameter test condition (in addition to those in table 8) min. max. unit i li input leakage current 2 ua i lo output leakage current 2 ua i cc1 standby current s # = v cc , v in = v ss or v cc 50 ua i cc2 operating current (read) c = 0.1v cc / 0.9.v cc at 50mhz, q = open 8ma c = 0.1v cc / 0.9.v cc at 20mhz, q = open 4ma v il input low voltage - 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.2 v v ol output low voltage i ol = 1.6ma 0.4 v v oh output high voltage i oh = -100 u av cc - 0.2 v .com .com .com .com 4 .com u datasheet
13 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 table 8. ac characteristics test conditions specified in table 4 and table 5 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read d.c. 50 mhz f r clock frequency for read instructions d.c. 20 mhz t ch 1 t clh clock high time 9 ns t cl 1 t cll clock low time 9 ns t clch 2 clock rise time 3 (peak to peak) 0.1 v/ns t chcl 2 clock fall time 3 (peak to peak) 0.1 v/ns t slch t css s# active setup time (relative to c) t chsl s# not active hold time (relative to c) t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s# active hold time (relative to c) t shch s# not active setup time (relative to c) t shsl t csh s# deselect time 100 ns 5ns 5ns 5ns 5ns note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. t shqz 2 t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t hlch hold# setup time (relative to c) t chhh hold# hold time (relative to c) t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx 2 t lz hold to output low-z 8 ns t hlqz 2 t hz hold# to output high-z 8ns 5 5 ns ns .com .com .com .com 4 .com u datasheet
14 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 figure 8. serial input timing c d s# msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 9. hold timing tchhl thlch thhch tchhh thhqx thlqz c q s# d hold# .com .com .com .com 4 .com u datasheet
15 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 figure 10. output timing lsb out addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv c q s# d .com .com .com .com 4 .com u datasheet
16 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 package information .com .com .com .com 4 .com u datasheet
17 p/n: pm1127 rev. 1.1, mar. 09, 2005 MX23L6454 revision history revision description page date 1.0 1. removed "preliminary" on page 1 p1 mar/02/2005 1.1 1. added "industrial grade" p 1,11 mar/09/2005 .com .com .com .com 4 .com u datasheet
MX23L6454 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. .com .com .com 4 .com u datasheet

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